This invention pertains to a clock recovery PLL (Phase Locked Loop) that generates a read clock for reading signals from a magnetic recording media or similar device based on the read signals read out from a magnetic recording media, optical disk or other recording media.
The clock recovery PLL generates a frequency signal (read clock) for the purpose of reading out the data that has been written to a magnetic or other media using a specific frequency signal (write clock).
In recent years, while recording media such as magnetic recording media and optical disks have made progress toward higher performance, lower costs are being sought. To lower costs, high performance LSI's, which are used in the peripherals of the recording media, have been sought.
FIG. 1 shows a traditional clock recovery PLL.
Based on the read signals read from the recording media and the write clock WCLK from the synthesizer PLL 1, the clock recovery PLL 10 generates a read clock.
The synthesizer PLL 1 is comprised of a 1/N frequency divider 2, a phase comparator 3, a charge pump 4, a loop filter 5, a voltage control oscillator 6 and a 1/M frequency divider 9.
The reference clock CLK is supplied to the 1/N frequency divider 2 and is divided 1/N times (where N is an integer) before being supplied to the phase comparator 3. At the same time, the signal that is generated by the VCO 6 is supplied to the 1/M frequency divider 9. The signal generated by the VCO 6 is divided 1/M times (where M is an integer) and is supplied to the phase comparator 3. At the phase comparator 3, the reference clock CLK, that was divided 1/N times is compared with the signal that was divided 1/M times. The compared signal is supplied to the charge pump 4 based on the compared phase error.
FIG. 2 shows an example of the phase comparator 3.
The phase comparator 3 is made up of 8 NAND circuits 20, 21, 22, 23, 24, 25, 26 and 29, the inverters 27, 28 and 31 and the AND circuit 30. A comparison is made between the reference clock (the reference clock that is divided 1/N times) and the comparison clock (the VCO 6 output signal that is divided 1/M times). Up signals and down signals, which are comparison signals, are outputted from the phase comparator based on the phase error. The up signals raise the frequency while the down signals lower the frequency.
FIG. 1 further shows the charge pump 4 supplying a signal based on the comparison signal to the loop filter 5. The loop filter 5 removes the high frequency component noise and flattens it, thereby supplying a smooth, flat signal to the VCO 6 as a return signal.
FIG. 3 shows an example of the charge pump 4. The charge pump 4 is made up of a current supply 31, PMOS transistors 32, 33, 37 and 38 as well as NMOS transistors 34, 35 and 36. The NMOS transistor 36 and the PMOS transistor 37 constitute the output stage of the charge pump 4; and they are controlled by the up signals and down signals from the phase comparator 3.
The VCO 6 is made up of a (V-I converter) voltage current converter 7 and a current control oscillator (ICO) 8.
FIG. 4 shows an example of the V-I converter 7. The V-I converter 7 is made up of an op-amp 39, a first NMOS transistor 40, a second NMOS transistor 41 and a resistor 42. The voltage Vi of the V-I converter 7 is inputted as the op-amp 39 and the current Io is outputted from the drain of the second transistor 41. The resistance of the resistor 42 is R. The current Io that is output can be expressed by the equation Io=Vi/R. The V-I converter 7 converts the voltage signal output from the loop filter into a current signal and is outputted to ICO 8 as the control current Ic.
FIG. 5 shows an example of the ICO 8. The ICO 8 is comprised of two PMOS transistors 43 and 44, a NMOS transistor 45, three CMOS transistors 46, 47 and 48 and three inverters 49, 50 and 51. The three CMOS transistors 46, 47 and 48 and the three inverters 49, 50 and 51 constitute the ring oscillator. The control current Ic outputted from the V-I converter 7 controls the value of the current of the three CMOS transistors 46, 47 and 48 and converts the frequency of the signal that the ring oscillator generates.
In this way, the VCO 6 adjusts the frequency of the signals generated based on the return signals from the loop filter 16 and outputs the write clock WCLK.
As shown in FIG. 1, the synthesizer PLL 1 locks the write clock WCLK at its initial frequency and the locked write clock WCLK is supplied to the clock recovery PLL 10. This PLL loop is the first PLL loop.
The clock recovery PLL 10 is made up of a phase comparator 12, a phase error detector 13, a selector 14, a charge pump 15, a loop filter 16 and a VCO 17. The configurations of the phase comparator 12, the charge pump 15, the loop filter 16 and the VCO 17 are the same as that which is shown in the synthesizer PLL 1.
The clock recovery PLL 10 contains the second PLL loop, which is made up of the phase comparator 12, the selector 14, the charge pump 15, the loop filter 16 and the VCO 17, as well as the third PLL loop, which is made up of the phase error detector 13, the selector 14, the charge pump 15, the loop filter 16, the VCO 17 and an AD converter (ADC) 11.
The second PLL is the same as the first PLL loop of the synthesizer PLL 1. The second PLL Loop performs the task of locking the read clock (RCLK) that is outputted from the timing recovery PLL 10 based on the initial frequency of the write clock WCLK that the synthesizer PLL 1 outputs. After the read clock RCLK, which is outputted by the timing recovery PLL 10, has been locked to the initial frequency, the selector 14 can be used to switch the second PLL loop to the third PLL loop.
The read signal is based on the read clock RCLK that has been locked to the initial frequency and the reading out of that signal begins in the third PLL loop. The read clock RCLK corresponding to the initial frequency is taken as a sampling clock. The ADC 11 samples the read signal from the recording media. The read signal is converted to a digital signal in the ADC 11 and is supplied to the phase error detector 13. The phase error detector 13 detects errors between the read-out timing of the read signal from the recording media and the read clock RCLK corresponding to the initial frequency. The phase error signal that is outputted by the phase error detector 13 is supplied to the VCO 17 via the selector 14, the charge pump 15 and the loop filter 16. The VCO 17 is made up of the V-I converter 18 and the ICO 19 just like the VCO 6 in the synthesizer PLL 1. The VCO 17 outputs a read clock RCLK with the error adjusted based on the phase error signal. The read clock RCLK that is adjusted based on the read signal is again supplied to the ADC 11 as a sampling clock and the read signal is sampled. In the third PLL loop, the error in the timing of the read signal sampling is repeated using the read clock RCLK and the error between the read clock RCLK that was adjusted based on the previously read out read signal and the read signal that was actually read out from the recording media is detected and the read clock RCLK is adjusted. Next, a read clock RCLK is generated that conforms to the read signal that was actually read out. This is how the third PLL loop performs its role of adjusting the differences in the timing between the read clock RCLK and the read signal that is actually read out from the recording media.
In order for the traditional timing recovery PLL 10 to lock the read clock RCLK, which is output from the timing recovery PLL 10, to the initial frequency of the write clock WCLK, the first PLL loop of the synthesizer PLL 1 and the second PLL loop of the timing recovery PLL 10 are necessary. For this reason, a double PLL loop configuration must be used, which increases the scale of the circuit. Time is also required for the double PLL loops to lock on to the initial frequency (lock up time), so it takes an extremely long time for the actual reading operation to begin.